Current multi-chip circuitry design requires the attachment of numerous integrated circuit chips to high density electrical interconnects, also known as multi-chip-modules (MCMs) or as substrates. The electrical interconnects normally include surface pads for bonding to surface mounted chips, a dielectric, and electrical lines buried in the dielectric for connecting selected pads to provide electrical routing between various bond sites on the chips. It is common to use copper for the buried lines and polyimide as the dielectric. The copper lines may form separate layers of orthogonal wiring sets that are interconnected to the surface pads by vertical metal pillars. Thus the construction of metal pillars becomes an essential part of the overall electrical interconnect fabrication process.
The fabrication of such electrical interconnects is a rapidly emerging technology with a number of different material and process options. While many processes have been proposed and put to use by a number of companies, there is typically a serious problem with yields since a substantial percentage of the interconnects are found to be defective. The yield problem is affected by the operator's expertise, choice of equipment, process characterization, and perhaps most importantly the adequacy of the fabrication process self.
For instance, if electroplating is used as one of the fabrication steps then pillar uniformity is likely to be an unavoidable problem. Photosensitive polyimide appears to be promising, but currently suffers from several disadvantages including limited resolution, limited via aspect ration, a high coefficient of thermal expansion (CTE), and a highly limited shelf life. Furthermore, if electroless metallization is used with photosensitive polyimide, the process control (e.g., electroless bath chemistry, wafer preparation, plating conditions) is usually unable to meet the pre-determined, non-flexible plating rate requirement. A disadvantage of conventional electroless via fill plating approaches is the difficulty in detecting when the electroless deposition is completed and the interconnect substrate can be removed from the plating bath.
Consequently, there is a need for better electroless via fill endpoint control.